As disclosed, for example, in U.S. Pat. No. 7,540,199 corresponding to JP-2008-20433A, a semiconductor device has been developed that includes a first substrate having a capacitive acceleration sensor and a second substrate having a piezoelectric pressure sensor. The second substrate is located to face, the first substrate and in contact with the first substrate so that a sealed space can be formed between the first and second substrates. The capacitive acceleration sensor is located in the sealed space.
Further, a through electrode is formed in at least one of the first and second substrates, and a wire connected to the through electrode is formed in the first substrate.
According to the above semiconductor device, when a layout of the wire formed in the first substrate is designed, there is a need to take into consideration a structure of a sensing section of the capacitive acceleration sensor. For example, in a layer where the structure of the sensing section is located, the wire needs to be laid out to pass between elements such as movable and fixed electrodes of the sensing section or to pass around the elements of the sensing section. Therefore, when the wire is laid out to extend parallel to a surface of the first substrate in the layer where the structure of the sensing section is located, the layout of the wire becomes complicated.